Tentative Lecture Lesson Plan

Week #1

• Course Introduction and Overview;
• Quick Tour through Design Process, Representations, and Technologies;
• AND, OR, NAND, NOR, XOR, XNOR;
• Motivation for Logic Simplification;
• Laws of Boolean Algebra and Switch Equivalents;
• Lab Lecture #1: Discussion of Hardware Laboratory #0
• Two Level Canonical Forms;
• Positive vs. Negative Logic;
• Readings: Katz/pp. 1-64.

Week #2

• Two Level Simplification;
• Boolean Cubes and Karnaugh Maps;
• Design Examples;
• 5 and 6 Variable Karnaugh Maps;
• Lab Lecture #2: Discussion of Hardware Laboratory #1
• Hardware Lab #0: Schematic Entry and Logic Simulation
• Readings: Katz/pp. 65-92.

Week #3

• Quine-McCluskey Method;
• Multi-level Logic;
• NAND-NAND and NOR-NOR forms;
• Lab Lecture #3: Discussion of Hardware Laboratory #2
• And-Or-Invert Gates; Multi-level Logic Synthesis with MIS;
• Tri-states and Open Collector Gates;
• Readings: Katz/pp. 111-136, 194-200.

Week #4

• Time Response in Networks;
• Combinational Hazards;
• Combinational Logic Word Problems;
• Lab Lecture #4: Discussion of Hardware Laboratory #3
• Circuits with State; Set-up and Hold Time; Simple Cross Coupled Gates: R-S Latch;
• Latches vs. Flip-flops;
• Timing Specifications;
• Hardware Lab #2: Digital ICs, LEDs, Propagation Delay, and Hazards
• Readings: Katz/pp. 92-101, 148-152, 137-147, 206-222, 275-285.

Week #5

• More Complex Sequential Circuits: RS-FF, D-FF, JK-FF, M/S-FF;
• Timing Methodologies: Cascaded Flip-flops + Set-up and Hold Times;
• MIDTERM I: Combinational Logic Design
• Lab Lecture #5: Discussion of Hardware Laboratory #4
• PALs and PLAs;
• Hardware Lab #3: Circuits with Feedback
• Readings: Katz/pp. 153-154, 285-294, 163-173, 294-300.

Week #6

• Design Examples;
• Multiplexers/Selectors and Decoders;
• Storage Registers, Register Files, Shift Registers, RAM;
• Realizing Circuits with Different Kinds of Flip-flops;
• Lab Lecture #6: Discussion of Hardware Laboratory #5
• Counter Design Procedure;
• Implementation with Different Flip-flop Types;
• Hardware Lab #4: Basic Latches and Clocking
• Readings: Katz/pp. 173-205, 301-303, 312-314, 325-349.

Week #7

• Alternative State Machine Representations: State Diagrams, ASM Charts,
• Hardware Description Languages;
• State Machines; Basic Design Procedure; Parity Checker Example;
• Lab Lecture #7: Discussion of Hardware Lab #6
• Moore and Mealy Machines: Implementation Examples;
• Hardware Lab #5: Registers, RAMs, and Busses
• Readings: Katz/pp. 355-370, 381-410.

Week #8

• Mapping Word Problems into State Diagrams: String Recognizer, Complex Counter,
• Mapping Word Problems into State Diagrams: Traffic Light Controller, Digital Combination Lock;
• Lab Lecture #8: Discussion of Hardware Lab #7
• Choice of Flip-flops; Implementation Strategies: ROM-based, PAL-based;
• Hardware Lab #6: Programmable Gate Arrays (Part I)
• Readings: Katz/pp. 411-430, 338-345, 471-488.

Week #9

• Implementation Strategies: Counters, EPLDs;
• Implementation Strategies: FPGAs, Xilinx LCAs;
• Lab Lecture #8: Final Project
• Finite State Machine Optimization: State Reduction Techniques
• Hardware Laboratory #7: Programmable Gate Arrays (Part II)
• Readings: Katz/pp. 495-544, 447-459.

Week #10

• Finite State Machine Optimization: State Assignment Techniques and Tools;
• MIDTERM II: Finite State Machine Design and Implementation
• Lab Lecture #9: Final Project
• Structure of a Computer; Interplay of Control and Datapath;
• Software Tutorial #3: State Assignment Tools
• LAB Project: Checkpoint #1, Preliminary State Diagram and Datapath Design
• Readings: Katz/pp. 460-485, 553-565;

Week #11

• Overview of Computer Hardware Organization and Register Transfer;
• Block Diagram/Register Transfer View; Memory Interface;
• Bussing Strategies; Influence on Control; State Diagram and Datapath for a Simple CPU;
• LAB Project: Checkpoint #2, Detailed Datapath Design
• Readings: Katz/pp. 566-588.

Week #12

• Derivation and Timing of Register Transfer/Microoperations;
• Controller Implementation: Classical Moore and Mealy Machines;
• Controller Implementation: Pure and Hybrid Jump Counters;
• LAB Project: Checkpoint #3, Detailed Controller Design
• Demonstration of Operational Datapath
• Readings: Katz/pp. 601-621.

Week #13

• Controller Implementation: Branch Sequencers and Microprogramming;
• Datapath Implementation: Number Systems
• Datapath Implementation: Simple Arithmetic Circuits;
• Carry Lookahead Logic and ALUs;
• LAB Project: Checkpoint #4, Testing Plan, Timing Diagrams
• Demonstration of Operational Controller
• Readings: Katz/pp. 622-637, 223-255.

Week #14

• Datapath Implementation: Multipliers;
• Self-starting Counters; Asynchronous vs. Synchronous Counters;
• LAB Project: Integration of Datapath and Controller
• Readings: Katz/pp. 256-267, 340-354.

Week #15

• Timing Methodologies: Narrow Width Clocking vs. Multiphase;
• Problems of Clock Skew;
• Asynchronous Inputs and Speed-Independent Circuits;
• Course Review;
• LAB Project: Demonstration of Working System to class
• Readings: Katz/pp. 294-300, 304-311.