LogicWorks(TM) Lab 3

NAND Synthesis and 5 variable K-Maps

1. Tutorial Objectives

In this laboratory, you will gain experience in using LogicWorks(TM) to create a new chip. Your job is to:

* Design the 2 bit adder using a Truth table and k-maps.

* Implement the 2 bit adder using a NAND Gate circuit with 3 gates of delay.

* Create a 2 bit full-adder chip with a carry in and out.

* Simulate the chip at the gate level.

* Use the device editor to make the 2 bit full adder chip.

* You do not need to show power and ground

* Your chip should be properly labeled (pin functions and title)

* Show timing diagrams and printouts for the chip.

* Make a library entry in YOUR OWN DIRECTORY with your adder.

* Submit hardcopy of the circuit used for simulation, the chip you made, and a timing diagram.

* Include this page as the cover sheet for your lab.

* You answer must include the following parts, numbered and in order:

1. Show the 5 variable K-Maps, with loops and Min SOP equations.

2. Rewrite the Min SOP equation to use NAND Gates ONLY

3. Implement the adder with NAND gates, show the printout of the gate level simulation you use to make the 2 bit full-adder.

4. Include a hardcopy of the chip used to implement your adder. Label the input pins: a0,a1,b0,b1,Ci. Label the output pins: C0,s1,s0.

5. Include a hardcopy of the waveform diagram.