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Instructions/Please Read Carefully!
In taking this examination, you agree that all work recorded herein is your own. A student caught in the act of cheating will be given a grade of F on this examination and a letter will be written to his or her file.
Read the questions carefully. If something appears ambiguous, raise your hand and ask, the exam may have bugs. Points have been assigned according to the formula such that 1 point = 1 exam minute, so pace yourself accordingly. There are 120 points on this test and you have 120 minutes to complete the exam.
All work is to be done on the attached sheets and under no circumstances are blue books or loose sheets to be used. Write your name at the top and do not proceed until your are told to do so.
Implement a Combinational Logic Design (15 points)
Implement a combinational logic circuit that converts a 4 bit sign plus magnitude number to the corresponding 4 bit 2's complement number.
First, complete the following truth table (3 points), Then fill in the following k-maps and write down the output functions in minimized sum of products form (3 points each):
Short Answer (10 points) Circle T if the statement is true, otherwise circle F for false.
1. Any Sequential Boolean function can be generated using demultiplexors. T F
2. A master/slave flipflop samples its inputs on one edge of the clock while it changes its output on the other edge. T F
3. Synchronous control inputs are sampled only on a clock edge. T F
4. The difference between a programmable logic array (PLA) and a programmed array logic (PAL) is that the former has an OR array that cannot be personalized while the latter does. T F
5. A read-only memory (ROM) can be viewed as a programmable AND/OR array in which the AND plane is programmed as a full decoder. T F
6. A Moore Machine usually has less states that an equivalent Mealy
Machine.
T F
7. The problem with a standard Mealy Machine is that its output changes are not synchronized to the changes in the clock. T F
8. A synchronous digital systems contains a single reference signal, the clock, such that all state memory changes are made with respect to the clock signal. T F
Fill in the blank with the correct answer:
9. The canonical POS form of an expression results in a __________level circuit. Assume that inverters do not count.
10. If you built a 128:1 multiplexer from 4:1 muxes, how many 4:1 muxes would you need?__________
11. Reverse Engineering (24 points)
Given the following implementation of a three-bit counter implemented with toggle flip-flops, derive the state transition diagram through the process of reverse engineering. Show all calculations to receive full credit!
Reverse Engineering Calculations:
TA= TB= TC=
Fill-in the State Transition Table:
Add the transitions to complete the State Diagram:
12. For the following pairs of numbers, if the sum of the numbers
results in a valid result in the given number system, write the equivalent base
10 result in the space provided. Otherwise, write "overflow" .(4 points)Twos
Complements:
Ones Complements:
13. (20 points) A MOORE sequential network has one input and one output. The output should be 1 if the total number of 0's received at the input is ODD and the total number of 1's received is an EVEN number greater than 0. This machine can be implemented in exactly six states. Complete the state diagram below :
Give a brief description of the partial strings recognized in each state
S0:
S1:
S2:
S3:
S4:
S5: Odd # of Zeros, Even # (>0) of Ones
14. In a carry lookahead adder, the correct equation for the carry input to the second stage (C2) is:(3 points)
(a)
C2=G1+P1C0
(b)C2=G0+P1C1
(c)C2=G1+P1G0+P1P0C1
(d)C2=G1+P1G0+P1P0C0
15. Match the circuit below with the phrase that best describes it from the list (5 points):
(a) clocked R-S latch
(b) clocked D latch
(c) master/slave R-S
flip-flop
(d) master/slave T flip-flop
16. Find the dual and complement of the following expression. (Do not simplify.) (5 Points)
F = [1 + (a + b')c + d'e'][f' + gh'(i + j)] + k*0
17 (4 points) Given that
,
Find the minterm expansion for F. 18. (15 Points) Your task is to implement
a finite state machine with TOGGLE flipflops given the following state diagram.
The FSM is a complex GRAY code counter with two control inputs, I1 and I0,
which determine the next state.
19. (15 points) Implement the following truth table, with inputs ABCD and with output X, using an 8:1 multiplexer. Assume that inputs ABC are to be used for selection. Please show work.
20. The following transistion table represents a sequential machine. It is to be realized with combinational logic and two J/K flip-flops. There is a single input, x, and a single output, Z. Determine the minimal boolean expressions for the inputs of the flip-flops and for the output.
J1=
K1=
J2=
K2=
Z=
Please check over your work, if you have extra time. Points are not awarded for tests handed in early. Good luck with your finals and have a nice break!